1. Field of the Invention
The present invention relates to a non-volatile semiconductor device, and, more particularly, to a sense amplifier used in a writing operation and a reading operation.
2. Description of the Related Art
Because non-volatile semiconductor memory devices have advantages such as data remaining intact even powered off, their demand is considerably increasing recently. A flash memory which is an electrically erasable non-volatile semiconductor memory device, unlike a bitransistor byte type non-volatile semiconductor memory device, has memory cells each of which can be constituted of a single transistor. This design can reduce the size of the memory cells, so that the flash memory is expected to replace a large capacity magnetic disk or the like. Those non-volatile semiconductor memory devices are designed in such a manner that a memory cell array has memory cells arranged in a matrix form, each cell constituted of an MOS transistor with a floating gate, and stores information in the form of the threshold value of the MOS transistor, which can be changed by accumulating charges in this floating gate. Since information writing and erasure are executed by supplying a current to the insulating film of the MOS transistor, the writing time considerably changes depending on variations in the fabrication process, use conditions and so forth. This is a significant difference between the flash memory and a DRAM or SRAM. Apparently, fast writing cells and slow writing cells coexist in the same chip.
To explain those shortcomings in detail, a NAND type flash memory as one example of such conventional non-volatile semiconductor memory devices will be discussed below.
FIG. 1 is a circuit diagram showing the cell structure of a NAND type flash memory. Non-volatile memory cells M1 to M16 each constituted of an MOS transistor having a floating gate are connected in series, with one end of the series circuit being connected via a select transistor Q11 to a bit line BL while the other end is connected via a select transistor Q12 to a common source line s. The individual transistors are formed on the same well substrate (well region) W. The control electrodes of the memory cells M1-M16 are respectively connected to word lines WL1 to WL16, the control electrode of the select transistor Q11 is connected to a select line SL1 and the control electrode of the select transistor Q12 is connected to a select line SL2.
The memory cells M1-M16 have threshold values corresponding to data they hold themselves; the threshold value is set greater than 0 V and smaller than 5 V when data "0" is held and the threshold value is set smaller than 0 V when data "1" is held. To be more specific, the threshold value is set smaller within a predetermined range to provide a certain margin.
FIG. 2 is a threshold value distribution diagram showing the distribution of the threshold values of the memory cells. In the case of the NAND type flash memory, the state of holding data "1" is called "erased state" while the state of holding data "0" is called "written state." Shifting the threshold value (Vth) of a memory cell holding data "1" in the positive direction so that data "0" is held is called "writing operation" and shifting the threshold value (Vth) of a memory cell holding data "0" in the negative direction so that data "1" is held is called "erasing operation." Those definitions may differ in the case of a NOR type memory cell.
FIG. 3 presents a table which shows voltages applied to memory cells having the structure shown in FIG. 1 at the time of executing the erasing and writing operations. In read mode, the bit line BL is precharged to 5 V to be in a floating state, followed by application of 5 V to the select line SL1, 0 V to the word line WL for the selected memory cell, 5 V to the word line WL for the unselected memory cells, 5 V to the select line SL2, 0 V to the well region and 0 V to the common source line S. Then, all the transistors except for the selected memory cell (including the unselected memory cells) are turned on. With data "0" held in the selected memory cell, this memory cell becomes nonconductive and the potential of the bit line is left unchanged to 5 V. When data "1" is held in the selected memory cell, on the other hand, this memory cell conducts so that the bit line is discharged and the potential drops. Sensing data is conducted by detecting the potential of the bit line at the time of data reading.
FIG. 4 is a threshold value distribution diagram at the time erasure of the memory cell in FIG. 1 is performed, FIGS. 5A and 5B are threshold value distribution diagrams at the time data is written in the memory cell. In erasing mode, the bit line BL is set free, 0 V is applied to the select line SL1, 0 V is applied to the word line WL of the memory cell, 0 V is applied to the select line SL2, 18 V is applied to the well region W and 18 V is applied to the common source line S. As a result, a tunnel current flows between the floating gate and the well region via the gate insulating film, and the threshold value becomes smaller than 0 V. FIG. 4 shows the shifting of the distribution of the threshold values.
In write mode, different voltages are applied depending on the data to be written. 0 V is applied to the bit line BL to write "0" (to shift the threshold value), while 9 V is applied to the bit line BL to write "1" (not to shift the threshold value). 11 V is applied to the select line SL1, 18 V is applied to the word line WL of the selected memory cell, 9 V is applied to the word line WL of the unselected memory cells, 0 V is applied to the select line SL2, 0 V is applied to the well region W and 0 V is applied to the common source line S. As a result, all the transistors from the selected transistor Q11 to that of the memory cell M16 conduct to have the same potential as that of the bit line (no consideration is given to a drop in threshold value of transistors).
Therefore, a high voltage of 18 V is applied between the channel and control electrode of the memory cell whose bit line BL is applied with 0 V, so that a tunnel current flows and the threshold value is shifted in the positive direction. Only 9 V is applied between the channel and control electrode of the memory cell whose bit line BL is applied with 9 V, thus suppressing the shifting of the threshold value in the positive direction. This 9 V is called "write disable voltage." FIGS. 5A and 5B show the shifting of those threshold value distribution.
As described earlier, non-volatile semiconductor memory devices perform data writing using the physical means called "tunnel current," so that the writing speed varies depending on the individual memory cells.
For slow writing memory cells, "0" is written at a certain time at which the threshold values of fast writing memory cells may exceed 5 V that is the upper limit for the "0" cells. In this case, data of the whole NAND cells cannot be read and the NAND cells become defective. That is, the control of the threshold values of the cells is the operational key point.
FIG. 6 is a circuit diagram of a conventional circuit for explaining the reading and writing operations on the memory cell in FIG. 1. FIG. 6 shows one bit line and each unit consisting of a plurality of NAND memory cells for diagrammatic simplification. Actually, several thousands bit lines are laid and NAND cells are laid in an array.
A flip-flop circuit (FF) comprises clocked CMOS inverters 1 and 2 whose active control is carried out by clock signals CK and BCK (inversion of CK), and temporarily holds written data. Connected to each bit line BL are NAND memory cells (MC) similar to those which have already been explained with reference to FIG. 1. Further connected to this bit line BL are a P channel transistor Q21 for charging the bit line BL and a transistor Q22 which connects the bit line BL to the FF circuit. Both ends of the FF circuit are connected to I/O lines 13 and 14 via a transfer gate.
Writing is executed in the following manner. The FF circuit is set active (CK is set to an "H" level) and data is written from the I/O lines 13 and 14. The FF circuit connected to the bit line BL corresponding to a cell to which "0" is to be written is set in such a manner that a terminal 15 connected to the bit line BL becomes "L" to turn on the transistor Q22. 0 V is applied to the bit line BL to write "0" in the selected cell. For the bit line BL corresponding to a cell which should be left holding "1," the terminal 15 is set to "H." At this point of time, the voltage of the source 16 of the PMOS transistor is set to 9 V to turn on the transistor Q22. 9 V is applied to the bit line BL, providing the same writing bias condition as shown in FIG. 3.
Reading is performed as follows. Referring to the waveform chart in FIG. 7, first, the FF circuit is disabled (CK is set to an "L" level) and the bit line BL is precharged to 5 V. Then, the transistor Q22 is turned on to set the control gate of the selected cell to 0 V and the control gates of the unselected cells to 5 V. Accordingly, the potential of the bit line to which the cells whose threshold values have exceeded 0 V are connected does not change, while the potential of the bit line to which the cells whose threshold values are equal to or smaller than 0 V are connected decreases with time in accordance with the cell current as indicated by a curve 18. By rendering the FF circuit active after a proper interval, e.g., at time t1, the potential of the bit line BL is latched in the FF circuit. More specifically, the voltage at the terminal 15 is latched to become "H" for data "0" and "L" for data "1."
FIG. 8 is a plan view showing the layout of the above-described memory cell array and a sensing circuit. A plurality of sense amplifiers 31, e.g., 4 K sense amplifiers, each comprising the aforementioned FF circuit are laid along one side of a memory cell array 32. Data of the cells in a row 33 are simultaneously input to the sense amplifiers 31. Data can be externally written in the FF circuits constituting the sense amplifiers to simultaneously write data in the cells of the row 33.
In some application, however, all the data of the cells of the row 33 should simultaneously be copied to cells of another row 34. This is called "copy back." Let us consider the case where this function is accomplished by using the sense amplifiers 31 of the conventional circuit. First, data of the row 33 are input to the sense amplifiers 31. At this time, the bit line terminal 15 for reading the memory cells holding "0" is detected to have an "H" level and the bit line terminal 15 for reading the memory cells holding "1" is detected to have an "L" level. When data is written in the cells of the row 34 under this condition, the bit line with the terminal 15 set to "H" has an intermediate potential so that nothing is written in the cells connected to this bit line, while "0" is written in the cells connected to the bit line with the terminal 15 set to "L." Consequently, even if the cells of the row 34 are in an erased state, inverted data is written in the cells of the row 34. That is, to precisely accomplish the copy back in the conventional circuit, it is necessary to simultaneously input data of the cells to the sense amplifiers 31 first, then read the data out to an external unit, invert the data and write the inverted data again in the sense amplifiers 31, and then simultaneously write the data into the cells. This system requires a data control unit outside and involves a considerable time loss of reading data from the memory cells and writing the data again into the cells.